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Power of GreenPower minimization has become a major design concern especially for smaller technology nodes, such as 65 nm and 45 nm. Global green initiatives to minimize carbon footprint has driven semiconductor vendors to define power limit for every design. Managing power effectively in a design flow has become extremely difficult since it involves tradeoffs such as timing-versus-power and area-versus-power at different stages of the design flow. Achieving this efficiently requires an integrated flow that addresses power concerns throughout the RTL-to-GDSII flow. Concurrent analysis and optimization is also critical for getting the best quality of results and minimizing design iterations. It is essential to have an open power format that can be used across the design flow and across different vendors for faster turnaround time.
In this demo, you’ll learn about Magma’s complete low-power IC implementation solution. We’ll show you how Talus Power Pro supports the proposed IEEE standard Unified Power Format (IEEE P1801 UPF). Advanced techniques including automated multi-voltage designs, ultra low-power clock tree synthesis, and physical implementation that meets 45-nm dynamic and leakage power requirements will be covered. Designers will also be exposed to the integrated sign-off engine, Quartz Rail, for power network integrity. Quartz Rail is an integrated power analysis solution in Talus Vortex and in the Talus Low-Power Implementation and Optimization flow, including early power analysis, transient IR-drop analysis and IR-drop-based timing analysis. Advanced analysis techniques such as switch-cell power-up analysis, insertion and optimization will also be covered.
Featured Products: Talus Power Pro, Talus Design, Talus Vortex, Quartz Rail
Days/Times:
Mon, Tue, Wed: 10:00, 11:00, 12:00, 1:00, 3:00, 4:00, 5:00Thurs: 10:00, 11:00, 12:00
Automated Hierarchical Design SolutionIncreasing design complexity is posing many challenges to designers today such as performance, power and area. In addition to these quality metrics, the sheer size makes it difficult to manage traditional tasks such as design partitioning, time budgeting, hierarchy management, block shaping, power planning etc. With time-to-market pressures shrinking the design time, the designers are looking for floorplanning tools to automate these traditional tasks and provide them with faster ways to achieve quality floorplans to close their designs.
Hydra, Magma’s stand-alone hierarchical design platform which enables hierarchical design planning and prototyping of designs using cutting-edge and automated technology to perform automated partitioning and shaping, optimized macro placement, enhanced global route-based pin assignment, accurate budgeting and black box handling. Hydra uses the same underlying engines for standard-cell and macro placement, physical optimization, timing and routing from other acclaimed Talus tools ensuring the quality and accuracy of floorplan created. This ensures that both the logic and physical design engineer can close on a solution faster.
This demo will show the Hydra solution, with the Quad-core hierarchical implementation of ARM’s® latest Cortex-A9™ MPCore™ embedded multicore processor. Highlighting Hydra’s new technology and features and its ability to provide hand-off quality floorplans in different stages of the design cycle, early prototyping to final implementation stages will be highlighted.
Featured Products: Hydra
Mon, Tue, Wed: 10:00, 11:00, 12:00, 1:00, 2:00, 3:00, 4:00, 5:00Thurs: 10:00, 11:00, 12:00
Best Physical Implementation Throughput Through Sign-OffAt advanced technology nodes (90/65/45), designers need to implement designs across multiple modes and process, voltage, temperature (PVT) corners. A physical implementation system needs to create a multicorner-aware, balanced and robust clock tree, physically implement the design across multiple modes and corners, and then allow for a fast and easy flow through sign-off. Low-power design practices must be integrated at all stages of the design, advanced routing rules must be supported and fast multithreading must be in use throughout all pieces of the flow. Massive design sizes make the use of stand-alone point tools painful and increase overall turnaround time. This demo will show low-power multicorner clock tree synthesis, concurrent physical implementation across multiple modes and corners and quick and easy sign-off integration on a 45-nm database. Magma’s industry-first memory-resident unique data model provides for the fastest throughput in getting advanced low-power high-performance multicorner/multimode designs through tape-out!
Featured Products: Talus Vortex, Quartz RC, Quartz Time, Talus qDRC
Accelerating Analog Circuit and Memory SimulationDesigning analog circuits and memories, whether standalone or embedded, requires accurate design and verification tools with speed and capacity. This demo will cover the benefits of FineSim SPICE and FineSim Pro usage in various types of analog IP and memory designs. One of the key topics discussed in this demo will be the impact of FineSim's native multi-CPU simulation technology on improving the design cycle time of complex memories and SiliconSmart’s automated characterization of embedded memories.
Featured Products: FineSim SPICE, FineSim Pro
Accelerating Mixed-Signal Design Even with today's "state-of-the-art" mixed-signal and full-custom design environments, the digital and analog design teams largely work in isolation with little or no visibility into what the other team is doing. It is not uncommon for the two domains to be first introduced to each other at the time of chip finishing, which is when the analog and digital blocks are placed and routed together. In this demo we will demonstrate how the Titan mixed-signal design platform provides a truly unified, automated, full-chip, mixed-signal design solution.
Featured Products: Titan
Accelerating Analog Design MigrationThe traditional analog/mixed-signal design environment has not changed in 20 years. Magma is offering design accelerators at all levels including device sizing and simulation. These accelerators, when used separately increase overall throughput/performance and when used together truly revolutionize current mixed-signal flows. If you want to port an analog design such as a PLL/PCI-Express/SERDES/ADC to 10 processes today, it will take you years. In this demo we will show how the Titan Analog Migration environment reduces the analog IP migration from years to weeks.
Mon: 10:00, 12:00, 2:00, 4:00Tues: 10:00, 12:00, 2:00, 4:00Wed: 10:00, 12:00, 2:00, 4:00Thurs: 10:00, 11:00, 12:00
Advanced Library and IP CharacterizationTypical IP components for SoC design are becoming increasingly complex as designers push to meet performance and power requirements. Traditional characterization and modeling solutions cannot keep pace with the functional complexity of these components, nor support the highly-accurate electrical models needed for 65-nm and 45-nm sign-off flows. This demonstration will highlight the accuracy, automation, and throughput of Magma's SiliconSmart characterization system when used to characterize custom cells, I/Os, and macros.
Featured Products: SiliconSmart
Mon: 11:00, 1:00, 3:00Tues: 11:00, 1:00, 3:00Wed: 11:00, 1:00, 3:00
Accelerating SoC Finishing and VerificationQuartz DRC, Talus and Titan Chip Finishing have been seamlessly integrated to drastically reduce the amount of time spent on chip finishing and physical verification tasks. In addition to cross probing Quartz DRC markers in the Titan or Talus environments, true integration allows blazing fast incremental DRC checks, visibility of base layers in the Talus environment, and fixing of systematic violations. These features (and more) also enable interesting flows only possible with tight integration such as pattern-based fill in the implementation environment, abstract validation, and accurate antenna checks.
Featured Products: Talus, Titan, Quartz DRC
Chip-Package Co-Design: Flip-Chip FinishingSystem-on-a-Chip (SoC) integration heralds a new era of package-aware place and route in which chip designers must consider substrate and PCB effects during implementation. As the chip size shrinks, I/Os increase in number and speed package-aware I/O bump placement becomes essential to reduce SoC implementation turnaround time.
In this demo, you’ll learn about RioMagic, a package-aware chip design tool that bridges the gap between packaging and chip design. We’ll show you how you can plan and implement the I/Os on the chip in the context of the package, optimize the I/O placement to concurrently satisfy the physical and electrical constraints in the chip and package, and complete constrained RDL routing and package-escape routing. By providing a single platform for chip-package co-design, RioMagic minimizes the number of iterations between chip and package teams.
In addition to chip-package co-design capabilities, we will show how to do the I/O cell assignment to the bumps, RDL routing, core bump planning for multiple voltage domains, routing to rail and via stapling.
Featured Products: RioMagic
Mon: 11:00Tues: 11:00Wed: 11:00
Chip-Package Co-Design: Package CentricSystem-on-a-Chip (SoC) integration heralds a new era of package-aware place and route in which chip designers must consider substrate and PCB effects during implementation. As the chip size shrinks, I/Os increase in number and speed package-aware I/O bump placement becomes essential to reduce SoC implementation turnaround time.
In addition to chip-package co-design capabilities, we will show how to read/change spreadsheet based bump/ball assignment and substrate routing feasibility for various package technology and prototype flows used for Requests for Quote analysis (RFQ).
Mon: 2:00Tues: 2:00Wed: 2:00
Chip-Package Co-Design: Flip-Chip Top-Down Planning/DesignSystem-on-a-Chip (SoC) integration heralds a new era of package-aware place and route in which chip designers must consider substrate and PCB effects during implementation. As the chip size shrinks, I/Os increase in number and speed package-aware I/O bump placement becomes essential to reduce SoC implementation turnaround time.
In addition to chip-package co-design capabilities, we will show how to explore multiple floorplan aspect ratios, different die sizes which are package and system aware to do the most optimal die size planning.
Mon: 12:00, 4:00Tues: 12:00, 4:00Wed: 12:00, 4:00
Chip-Package Co-Design: JapanesePlease note: This demo will be presented in Japanese.
System-on-a-Chip (SoC) integration heralds a new era of package-aware place and route in which chip designers must consider substrate and PCB effects during implementation. As the chip size shrinks, I/Os increase in number and speed package-aware I/O bump placement becomes essential to reduce SoC implementation turnaround time.
In addition to chip-package co-design capabilities, we will also show how the design flows between package synthesizer CR-5000 and RioMagic, and how systems-aware chip design works.
Mon:10:00, 3:00Tues:10:00, 3:00Wed:10:00, 3:00Thurs:10:00
Enhancing Yield through Integrated Yield ManagementMany sources contribute to yield and device loss. Pinpointing the causes of lower yields requires both integration of software tools and analysis methodologies to sift through the terabytes of information to find root cause. Magma will demonstrate the latest offerings for device debug and failure analysis (FA) with its flagship Camelot software solutions and options. In addition, a review of the Magma integrated fab-wide yield management system, Yield Manager, will be presented along with LogicMap for true design for manufacturability (DFM).
Featured Products: Camelot, Yield Manager, LogicMap
