Jump to content
Magma Magma Design Automation (Canada, E.U., Japan, Korea, Taiwan and U.K.) Blast Chip (U.S. and U.K.) Blast Fusion (U.S., Canada, E.U., Japan, Korea, Taiwan and U.K.) Blast Gates (U.S. and E.U.) Blast Noise (U.S. and E.U.) Blast RTL (U.S.) Blast Speed (U.S., E.U., Japan, Taiwan and U.K.) Blast Wrap (U.S.) FixedTiming (U.S. and Japan) MegaLab (U.S.) Melting Logical & Physical Design MOLTEN (U.S., Canada, E.U., Japan, Taiwan and U.K.) QuickCap SiliconSmart Talus YieldManager (U.S.)
ArchEvaluator Automated Chip Creation Blast Create Blast DFT Blast FPGA Blast Logic Blast Plan Blast Power Blast Prototype Blast Rail Blast SA Blast View Blast Yield Camelot Characterization-to-Silicon Design Ahead of the Curve Diamond SI Fastest Path from RTL to Silicon FineSim FineWave GlassBox HyperCell MagmaCast Merlin Native Parallel Technology PALACE Physical Netlist Quartz QuickInd QuickRules Relative Floorplanning Constraints Relative Placement Constraint RioMagic Sign-off in the Loop Silicon Integrity (U.S., E.U., Japan, Korea and Taiwan) SiliconSmart CR SiliconSmart I/O SiliconSmart MR SiliconSmart SI Smart Sampling SuperSite Titan Volcano
Copyright information