This physical design environment enables rapid development of netlist- and chip-level constraints throughout the design process and delivers improved timing and signal integrity, smaller area, lower power, better manufacturability, faster turnaround time and higher capacity than conventional point-tool flows.  

This fully scalable physical verification solution leverages a unique architecture and advanced modeling capabilities, allowing affordable massively distributed processing of DRC and LVS comparison. It integrates inherent DFM knowledge into physical verification to deliver better results.