Titan Chip Finishing

Titan™ provides an integrated chip-finishing solution for mixed-signal designs. The unprecedented level of integration and automation provided by Titan enables significant increases in productivity by eliminating the potentially time-consuming and difficult iterations between traditional custom-layout and standard-cell implementation systems. Titan Chip Finishing includes a layout editor, a shape-based custom router, complete encapsulation of the Talus® digital design solution and integrated Quartz™ DRC and Quartz LVS verification solution.

Includes the fastest, highest capacity and smallest memory-footprint layout editing system to handle large full-chip designs.
Full-featured custom layout editor allows all chip finishing layout tasks such as reticle planning, critical dimension structures, alignment targets and scribe lines, flip-chip bump connections, 45-degree routing emulation and top-layer routing for the entire design.
Analog and special-signal shape-based routing provides speed, repeatability and ease of engineering change order (ECO) implementation.
Standard-cell digital design implemented in Talus or Blast Fusion® is fully encapsulated within Titan through a live interface, enabling designers to perform custom additions and edits to the standard-cell digital design.
DRC and LVS checks using Quartz and other industry-standard physical verification solutions are fully encapsulated within Titan, providing designers ease of both full custom and standard cell corrections.

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