Design for Manufacturability

Magma leads the industry with a comprehensive characterization-to-silicon DFM-aware flow

To achieve acceptable performance and yield goals at the 65-nm technology node and below, a true DFM-aware environment is required. This environment must account for process variability and lithographic effects in the context of timing, power, noise and yield at every stage of the flow. This begins with the characterization of the cell library; it continues through implementation, analysis and optimization, and sign-off verification; and it ends with failure analysis in the fab.

Magma is leading the industry with a comprehensive characterization-to-silicon DFM-aware flow. Key components of this flow include:

SiliconSmart® DFM enables designers to tackle both systematic and random process variations. By reducing reliance on guard-banding techniques such as on-chip variation and by guiding the selection of higher-yielding cells, SiliconSmart DFM allows designers to increase yield.
Quartz^TM DFM quickly detects and surgically fixes areas of the layout that affect performance and yield. It uses foundry-certified analyses to detect areas of the layout with printability problems and executes automatic fixing recipes to ensure an error-free design.
Camelot imports CAD design data from all the key LVS packages and several user-proprietary formats and provides visual representations of circuits, converts layout, netlist and schematic data, and establishes crossmapping links between each data entity. By allowing failure analysis engineers to collect, analyze and share this information with designers, Camelot allows closer collaboration between product and design groups with failure analysis labs and improves time to yield and market.
YieldManager combines high-level correlations of disparate data sources with the rapid drill-down of data scope to expedite identification of the root causes of yield loss, saving engineering time and focusing resources.