Blast Create

Blast Create™ provides a predictable path from RTL to placed gates. It is a unified environment for general logic and high-performance datapath synthesis, DFT analysis and insertion, physical synthesis, power optimization and static timing analysis. The Physical Netlist™ (placed gates) generated by Blast Create provides a clean handoff between the RTL designer and the layout engineer, eliminating time-consuming layout-to-synthesis iterations for timing closure.

Full-featured, high-capacity, IEEE LRM-compliant RTL synthesis engine enables rapid exploration of design space with clean handoff to the full-chip implementation flows, and provides a predictable path to design closure.
Built-in datapath engine provides state-of-the-art datapath synthesis capability for high-performance and compute/arithmetic intensive designs. Micro-architecture swapping is enabled throughout the flow ensuring better QoR for datapath intensive designs.
Fast, detailed placement and global routing of entire design enables implementation of multimillion cell chips and ensures predictable timing closure.
DFT technology provides a comprehensive solution for early testability analysis, scan insertion and automatic repair of DFT-related problems across the entire implementation flow.
Early RTL, structural and DFT checks result in accelerated problem detection and fixing, delivering sign-off-quality RTL and providing a clean ASIC handoff model.
”What-if” analysis of speed-vs-accuracy tradeoffs, partitioning decisions and identification of problems within RTL and constraints is accomplished through user controllable options or synthesis, placement, interactive editing and cross-probing capabilities.
An integrated design flow, single executable, common analysis engines and a unified data model enhance productivity, provide ease of use, eliminate unnecessary file transfers and ensure continuous correlation to final implementation.
Compatible with industry-standard coding styles, constraints and parasitic file formats.
Unified solution eliminates time and effort migrating the design between point tools.
Fully integrated structured ASIC option to enable low-cost ASIC designs.

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