Blast Fusion

Blast Fusion® is an advanced netlist-to-GDSII chip implementation system for high-performance, high-complexity and low power designs being implemented in 90-nm and finer process geometries. Blast Fusion delivers complete design closure with better timing, smaller area, lower power, better yield, faster turnaround time and higher capacity than conventional point-tool flows.

Super-high capacity allows designs of up to 5 million gates to be implemented flat on a 32-bit Linux machine, or up to 6 million gates to be implemented flat on a 64-bit Linux machine.Faster runtime is achieved through unified engines and efficient algorithms. 2-milliongate designs can be completed overnight.
Unmatched timing and area results are enabled through the FixedTiming® methodology, SuperCell™ abstraction, integrated clock tree technology, OCV analysis and optimization, and concurrent multi-mode and multi-corner analysis and optimization.
Significant leakage and dynamic power reduction is achieved through an integrated implementation flow using multiple threshold voltage (multi-Vt) cells and multiple voltage support, without sacrificing performance.
Proven 90-nm design support for major silicon vendors and foundries is provided through design rules and design-formanufacturability capabilities.

Product Index
Request Information
Featured Resources
- White Papers
  - Automated Chip Creation
  - Package-Aware I/O Planning
- Webinars
  - Fastrack/Talus ACC
Featured Products