Digital Design

Magma's digital design solution provides unequaled automation and scalability, delivers better results

The Talus® implementation system provides a fully integrated RTL-to-GDSII flow for high-performance, high-complexity, low-power nanometer designs that includes: synthesis, optimization, placement, routing, useful skew clock generation, floorplanning and power planning, incremental RC extraction and a single incremental timing analysis engine. Built on Magma’s unified data model and combined with optional automated distributed processing on multiple computers, Talus enables any size design to be implemented from RTL to GDSII in a predictable fashion.

At 65-nanometers and below new design challenges and tougher time-to-market requirements cannot be addressed by traditional point-tool flows. Designers need an integrated full-chip synthesis methodology that addresses all aspects of the design flow, eliminates time-consuming manual work, prevents the introduction of new errors – especially for changes that must be made late in the design phase – and ensures design closure.

Following are key components of Magma’s integrated and automated digital design solution:

Talus Design is a full-chip synthesis environment that enables rapid development of RTL and chip-level constraints throughout the design process, and automates data-path synthesis and floorplan generation for prototyping.
Hydra is an auto-interactive floorplanning and hierarchical design planning solution featuring a complete physical optimization capability that enables accurate floorplan handoff. It is a standalone solution that is also fully integrated into Magma’s RTL-to GDSII flow, enabling designers to manage the complexity of multimillion-gate designs to reliably achieve timing closure.
Talus Vortex is a physical design environment that enables rapid development of netlist- and chip-level constraints throughout the design process and delivers improved timing and signal integrity, smaller area, lower power, better manufacturability, faster turnaround time and higher capacity than conventional point-tool flows.
Talus® qDRC enables sign-off-quality design rule checking within the implementation environment. It allows visibility into reference-level IP views with all GDSII layers, making debugging easy. The incremental mode handles engineering change orders (ECOs) in seconds, operating on only those QuickCap NX portions of the design that changed.