Talus ACC

Talus® ACC, a key component of Magma's Automated Chip Creation™ platform, operates within the Talus physical design environment that allows rapid development of RTL- and chip-level constraints throughout the design process without sacrificing design quality or delivery schedule. This environment dramatically improves designer productivity by automating top-down chip planning, floorplan generation, physical block shaping and partitioning, distributed block closure and automated top-level chip closure. These capabilities – combined with optional automatic distributed processing on multiple computers, the automated synthesis capabilities of Talus Design and physical implementation capabilities of Talus Vortex – enable any size design to be implemented from RTL to GDSII in a predictable fashion.

True top-down flow eliminates need for block design and manual floorplanning, and enables late-arriving specification changes in the netlist or constraints without schedule impact.
Fully automated floorplanning enables rapid exploration of design space and the physical implementation flow, and provides a predictable path to design closure.
Automated hierarchy management, physical partitioning, macro placement and soft block shaping improve chip utilization by 10 percent across a wide range of SoC designs.
Relative Floorplan Constraints eliminate manual intervention when changes need to be made in logical hierarchy or size and shape of physical partitions.
Integrated design flow, single executable, common analysis engines and a unified data model enhance productivity, provide ease of use, eliminate unnecessary file transfers and ensure continuous correlation to final implementation.

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