Talus Vortex

Talus® Vortex is a physical design environment that enables rapid development of netlist- and chip-level constraints throughout the design process without sacrificing the quality of design or delivery schedule. This environment dramatically improves the productivity of physical designers by automating floorplan generation and complete design closure.This integrated implementation and sign-off system delivers improved timing and signal integrity, smaller area, lower power, better manufacturability, faster turnaround time and higher capacity than conventional point-tool flows. These capabilities, combined with optional automated distributed processing on multiple computers, enable Talus Design and Talus Vortex to implement any size design from RTL to GDSII in a predictable fashion.

Fully automated congestion-aware macro-placer flow and optimization technology enable rapid exploration of the design space and provide a predictable path to design closure.
Significant improvement in ROI due to 10 percent reduction in area, 5-10 percent improvement in performance or 30-50 percent reduction in power consumption.
Unmatched timing and area results are enabled through an efficient delay model, integrated clock-tree technology, concurrent multi-mode and multi-corner analysis and optimization with integrated crosstalk prevention, and native on-chip variation (OCV) inclusion.
Significant leakage reduction is achieved through an integrated implementation flow using multiple threshold voltage (multi-Vt) cells, without sacrificing performance.
Embedded sign-off accuracy (with Quartz™ RC and Quartz Time) for extraction, timing and noise eliminates post-layout analysis and repair iterations through third-party tools.
Integrated design flow, single executable, common analysis engines and a unified data model enhance productivity, provide ease of use, eliminate unnecessary file transfers and ensure continuous correlation to final implementation.
Proven 90-, 65- and 45-nm design support for major silicon vendors and foundries.

Product Index
Request Information
Featured Resources
- White Papers
  - Automated Chip Creation
  - Package-Aware I/O Planning
- Webinars
  - Fastrack/Talus ACC
Featured Products