Talus qDRC

Talus® qDRC is an integrated physical design verification tool for direct use during implementation. Using foundry-certified design-rule runsets, Talus qDRC increases productivity by providing sign-off quality DRC from within the implementation environment. Visibility to reference-level IP views with all GDSII layers makes debugging easy. The incremental mode handles ECOs in seconds, operating on only those portions of the design that changed.

Sign-off quality DRC from within the implementation flow eliminates costly stream-out methodology for DRC-clean results.
Foundry-certified, sign-off design rule runsets are available from all the major foundries.
Calibre runset translator reads design rules for use in the Talus implementation flow.
All-layer view eliminates base-layer alignment issues without leaving the Talus environment.
Identifies cell fill errors early for debug.
Incremental operation checks only the changed parts of the design for fastest turnaround – no full GDSII-to-GDSII comparison is needed.
Short finder locates multiple shorts in nets for debug.
Debugging viewer and easy correction scripting facilitate design updates.
Provides access to reference-level IP view.
Operates directly on a Volcano™ data model to maintain data integrity.
Pipelined architecture scales linearly with the addition of more CPUs for shorter execution times.
Incremental mode makes correction to only the changed portions of the design, saving time.

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