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Talus ATPG: Physically Aware Test Development As designs move to smaller nanometer processes, test development is becoming more difficult, effectively impeding product release. Not only are test sets growing at a very high rate, but they are unable to provide adequate levels of coverage that older metrics such as static, stuck-at fault coverage used as a measure. Now, the actual value and quality of a set of test vectors depends upon many other factors. One of the first signs that more test types were required appeared when early adopters of the 130-nm processes also were early movers towards timing-based testing. They had to make the transition due to the number of test escapes they were seeing compared to the earlier processes. As the industry moves to smaller feature sizes, even more complicated tests will become necessary.
In this white paper, we’ll describe the technology behind Talus ATPG and Talus ATPG-X with on-chip compression. You’ll learn how this advanced software enables designers to significantly improve test quality, reduce turnaround time and cut costs of nanometer ICs. Integrated into the Talus physical design environment and leveraging a single data model, Talus ATPG and Talus ATPG-X support virtually all current fault models, scale easily to support future models and provide a physically aware DFT flow.
ARM and Magma: Managing Low Power Designs - Library and Design Flow Handheld consumer devices are driving the demand for ICs with more functionality, higher performance, smaller package sizes and lower power requirements. At least three aspects of design implementation must be well understood to address power – library/process, architecture and tools/design flow. In this webinar, we address these three aspects as a joint presentation with the ARM® low-power architecture, ARM standard-cell libraries and Power Management Kit, and Magma’s low-power extension to the existing ARM and Magma reference methodology. View this webinar now and learn how ARM and Magma provide the low-power tools and methodology you need to help reach your design goals.
Fastrack – Magma Case Study: Implementing Large and Complex 65-nm ASICs in the Magma Flow In this webinar, Fastrack Design describes the implementation of a high-performance, 65-nm ASIC using the Magma flow. Synthesis, virtual prototyping, optimization and design for manufacturability (DFM) are discussed, as are techniques to produce consistent and predictable results while meeting all design goals. Finally, some of the implementation and tool challenges within 65-nm design are highlighted.
FineSim SPICE and FineSim Pro: Predict Performance for Any Design with SPICE-level Circuit Simulation At advanced process nodes it is much more difficult to predict device performance - which is why Magma offers the FineSim family of circuit simulators, FineSim SPICE and FineSim Pro. These SPICE-level simulators accurately and quickly predict circuit functionality for any size design early in the design cycle so you can make the adjustments necessary to ensure silicon success. View this webinar and learn how FineSim Pro and FineSim SPICE can help you reach your design goals.
Virage Logic – Magma: Managing Power with a Complete Physical IP and Design Flow The Virage Logic-Magma low-power reference methodology utilizes Magma’s Blast Power to implement a number of power reduction techniques including support for designs with multiple supply-voltage domains, concurrent multi-VT optimization, power gating with MTCMOS, clock gating and multi-mode analysis and optimization. Magma’s Blast Rail NX has been incorporated in this reference methodology to provide static, dynamic and transient power and voltage-drop analysis.View this webinar and learn how Virage Logic and Magma provide the low-power tools and methodology you need to help reach your design goals.
Rajeev Madhavan Talks with John Cooley about Titan and More In this interview, Rajeev announces "Titan", his new Virtuoso-killer, along with discussing Pcells, Ciranova, PDKs, Analog Artist, Talus, Mojave, QuickCap, Quartz-TLX, OA, MatLab, process migration, Sagantec, "AnalogWare", Cosmos, Pulsic, fabs, 65 nm, 45 nm, the Synopsys-Magma lawsuit, Jay Vleeschhouwer, bean counters, Cadence, and Mentor Calibre.
Improving Test Quality at 65 nm and Below with Talus ATPG The increased complexity and smaller feature sizes of today's chip designs make it more complicated to test manufactured ICs. Traditional test approaches lack the performance, accuracy and capacity to deliver the required level of test quality and turnaround time for nanometer ICs. View this demo to learn how Magma's advanced Talus® ATPG and Talus ATPGX software allows designers to improve test quality and turnaround time.
Using Magma’s Flow for Designing eASIC Structured ASICs In this webinar, we describe how Magma’s Blast Create™ and Blast Fusion® provide a completely integrated RTL-to-GDSII flow for eASIC’s revolutionary Nextreme structured ASICs. You see how the Magma flow is used for implementing single-chip customized embedded systems containing soft 32-bit processors such as the ARM926EJ and OpenCores OpenRISC1200. We cover clock generation, memory placement, I/O assignment, pre-synthesis design rule checking, synthesis, placement, optimization, routing and verification. Finally, you see how customers from a variety of vertical markets are using Magma’s design flow and eASIC’s Nextreme structured ASICs to cut production costs and speed time to market.
Managing Power and Performance with the ARM11 MPCore and Talus IC Implementation Flow Embedded multiprocessing sub-systems are replacing uniprocessors to meet performance requirements of the latest hand-held consumer devices. These multicore systems have proven to deliver better MIPS/MHz, MIPS/mW and MIPS/mm2 than comparable uniprocessors, and to offer more effective power management without the need for expensive IC process technologies or heat removal techniques. In this webinar, we show how to implement the ARM11 MPCore using Magma’s Talus® Implementation Flow to better manage system power and boost performance. You see how the ARM11 MPCore design can be implemented with full control over power, both dynamic (via multiple-voltage-island optimization) and leakage (with power gating) using the integrated and automated low-power design capabilities within Magma’s Talus IC implementation platform.
Yield Enhancement Using Logic Mapping — a Fab Perspective Knights LogicMap™, an option to Knights YieldManager™ yield-management software, is the industry’s first commercially available software solution for correlating inline defects with failed nets in a logic device. This webinar outlines how to utilize Knights LogicMap and Intensity Map software to find the root cause of defects within a logic device. We show how implementation of a LogicMap data infrastructure, automation of data inputs/outputs and aggressive application implementation can provide extremely successful correlations to inline defects and hit rates of defect locations for a rapid return on investment.
Talus qDRC: Eliminate Surprises with Sign-off Quality Verification Throughout the Flow Shrinking geometry sizes and increasing design rule complexity require that physical verification be performed earlier in the flow. Talus qDRC makes available the sign-off accuracy and speed of Quartz DRC to every engineer currently using Talus. In this webinar, you see the necessary one-time configuration, including a handful of convenient customization options. We highlight a handful of convenient ways of browsing design rule violations, along with how to use the incremental mode, which runs only one the layers and sections of the design that have changed.
TSMC/Magma: Addressing DFM with Magma Software Qualified for TSMC’s Reference Flow 8.0In this webinar you’ll learn how to address DFM issues at the 65-nm and 45-nm design nodes with Magma software and TSMC’s Reference Flow 8.0, with the emphasis on managing DFM effects like chemical-mechanical polishing (CMP), lithography process checks and critical-area analysis. We discuss the impact of new electrical rule checks, which are becoming more important at 65 and 45 nm. Finally, we demonstrate Magma’s complete flow qualified for the TSMC Reference Flow 8.0.
Podcasts
MagmaCasts are podcast audio interviews with Magma product experts. Click on a link below to listen on your computer or download for your iPod or other MP3 listening device.
Circuit Simulation: FineSim SPICESuk Lee, General Manager of Magma’s Custom Design Business Unit, explains how FineSim SPICE brings the benefits of circuit simulation to much larger, more complex SoCs than previously possible. Host: Milan Lazich
Physical Verification: Quartz DRC and Quartz LVSJohn Lee, General Manager of Magma’s Physical Verification Business Unit, talks about the sea changes that are necessary in physical verification and what makes Quartz DRC and Quartz LVS the “next big thing” in this field. Host: Milan Lazich
Predictable SynthesisYatin Trivedi, Product Director in Magma’s Design Implementation Business Unit, discusses the technology changes that make it necessary to adopt predictable synthesis, as provided in Blast Create. Host: Milan Lazich