Jump to content
论文摘要
Papers
A Fast Macro Placement Methodology Based on the Logic Group
Implementing a System on Chip (Soc) using Talus®
A Simulation Strategy for NAND Flash Memory by using Finesim™
Timing Closure Techniques for Challenging Partitions
Accelerating Analog IP Design with Parallel Spice Tools: The Design of WideBrand PLL with a Single Power Supply
Handling Big Engineering Change Orders (ECOs) at the Post-Optimization Stage
A Symmetrical Power Structure for the Repeated Blocks of a Hierarchical Design
Several Ways to Solve Congestion Issues on Two, Large 65-nanometer (nm) Designs with Magma
Dealing with Timing Closure Challenges on a 65nm Design
Clock Design and Analysis for a 40-nm, 500-MHz DSP Core
How to Implement 32 LPCAMs in 65-nm Chip using Magma
Tutorial
Solving Design Challenges Visually with the Talus Visual Volcano
内容摘要：The paper introduces a fast floorplan method for high macro count and hard timing design. Magma talus can generate a quick placement for all macros and standard cells based on logic group, then we can use this placement info to highlight and divide appropriate “macro group”, which is faster and more reasonable than normal group method for high macro count design. For hard timing design, we can use aggressive “macro placement” method to show the critical logic group then tune the placement shape (keep critical logic close together without macro and other logic group blocking) by incremental “macro placement”. This method can lead to better timing (both WNS/TNS) and better routing result (total wire length) for our regular design.
题目： Timing Closure Techniques for Challenging Partitions 作者： Di Ma and Vito Wu, Nvidia内容摘要: Timing closure is always a major issue in high performance processors. Usual techniques such as size-up, inserting buffer and useful skew may not be sufficient to solve the violations in certain cases. This article will discuss some techniques that were used in previous deep sub micron projects. They are beyond usual techniques and may only be applied to special cases. These areas will be involved: predict potential partition boundary timing issue, incremental placement iteration, clock gating clone strategy selection, use wire delay to minimize delay difference under different timing corners.
题目: Accelerating Analog IP Design with Parallel Spice Tools: The Design of WideBrand PLL with a Single Power Supply作者： Zhuo Ma and Jihua Chen, Central South CAD Center内容摘要: For phase-locked loop(PLL) design, circuit simulation is a time-consuming step. Iteration Speed fully depends on how fast of each simulation cycle. A certain PLL, which employed in a type of embeded CPU, was established on 0.13μm CMOS process, with wide band reference clock from 10MHz to 100Mhz and output clock from 50MHz to 900MHz. Obversly, a lot of simulation work is needed in design course, including a hundred of simulation corner. The tradditional methods or spice tools could not handled such a huge workload in a definite time. With the help of parallel spice tool, FINESIM, a tool provided by MAGMA, the simulation phase was rapidly shortened. With this tool, a multithreading/multiprocessing method was employed, and the speed-up is over 3.
题目: Handling Big Engineering Change Orders (ECOs) at the Post-Optimization Stage 作者： Zhang Lei and Chandler Mei, Nvidia 内容摘要: In this paper, we discuss how we handle big ECOs at post-optimization stage. At post-optimization stage, most optimize steps have been done. We don’t want to redo the previous optimization steps. In order to achieve this object, we need to apply these ECOs more intelligent and affecting other things as less as possible. We’ll discuss some kind of big ECOs we met in project, and introduce how we handle them by Magma. The paper will cover adding/moving big macros at post-optimization stage, rebuilding buffer tree for reset nets and refining eco placement for big functional eco. We’ll look into these issues and compare different ways to implement it.
题目 A Symmetrical Power Structure for the Repeated Blocks of a Hierarchical Design 作者： Tony Ku, Global UniChip内容摘要: In some ASIC, the function blocks will be instantiated in multiple times, like DDR and network design. These reused function blocks should be implemented once and then cloned the content to other blocks to reduce the implementation period. But if the reused blocks inherit the different power structure in the different location, these blocks cannot be treated as the repeated blocks. So we propose a symmetrical power structure methodology to maintain the power structure in each repeated blocks regardless the floorplan. In this methodology, we create a symmetrical power structure in a floorplan unit. This floorplan unit is a multiple of the Metal2 and Metal1 grid and modifies the initial offset to align the metal grid. Then, in the partition step, we force the partition block's floorplan (shape) to be the multiple of the floorplan unit. In the result, the repeated blocks can be placed in any location and mirror in any axis.
题目: Several Ways to Solve Congestion Issues on Two, Large 65-nanometer (nm) Designs with Magma 作者： Yang Zhang, Rabby Xiao and Tommy Liu, Texas Instruments内容摘要: Congestion and routability are major design closure issues hampering today's complex designs at 65nm and below. Congestion affects both the performance (area, timing, power) as well as the yield of the SOC. This paper discribe the analysis of the real congestion problems which we met during two 65nm big designs. Also discribe the reason and solution of these issues. These ways including backend level and also upper levels.
题目: Dealing with Timing Closure Challenges on a 65nm Design 作者： Tommy Liu, Dell Liang and Yang Zhang, Texas Instruments内容摘要: Timing closure is the major challenge for current high-speed, complex ASIC design. This paper will not try to address extensive timing closure problems, it will share some experience on one actual 65nm design with magma tools, including the early timing analysis, multi-mode/multi-corner optimze and how to reduce the cycle time of ECO.
题目: Clock Design and Analysis for a 40-nm, 500-MHz DSP Co作者： Rabby Xiao and Yang Zhang, Texas Instruments内容摘要: This paper presents a clock tree design method which greatly improve the QOR of Magma cts. This method has been proven to achieve 50ps clock skew across different PTV conditions by driving over 53k flipflops. The method greatly help in reducing clock cycle time and improving tolerance to process variations for high frequency designs in 40nm.
题目: How to Implement 32 LPCAMs in 65-nm Chip using Magma 作者： Jinyu Guo, Texas Instruments内容摘要: LPCAM is different from normal memory. Its size is tall and narrow, Pin count is up to 1024. Other than this, There are some routing blockage on Metal5. It cause severity congestion and bad timing. The paper introduce the method to solve the congestion issue and timing issue using Magma.
Solving Design Challenges Visually with the Talus Visual Volcano Presenter: Rob Knoth, Technical Product Manager, Magma While IC design complexity increases, engineering teams have remained the same size or have shrunk. Today’s engineers have to be exponentially more productive to get their jobs done. Talus Vortex helps improve designer productivity by delivering improved timing and signal integrity, smaller area, lower power, better manufacturability, faster turnaround time and higher capacity than conventional point-tool flows. But things don’t always go according to plan and schedule. To accelerate design debugging and improve communication between team members, Magma provides the Talus Visual Volcano™. This visual analysis environment integrates and presents all design and analysis data via a common display, allowing you to make better design decisions faster. In this presentation, we’ll show you how the Talus Visual Volcano allows you to: